LOCATION : Bangalore
EXPERIENCE : Freshers
QUALIFICATION : B.E/B.Tech/M.E/M.tech
The candidate should be a B.E/B.Tech/M.Tech(Electronics/Electrical/allied subjects)graduate from any recognized university.
Should have secured minimum marks of 70 % or CGPA of 7.0 and above, in aggregate of all semesters through out the academics.
The candidate should have the aptitude to work in the VLSI domain.
Should possess good communication skills and is able to demonstrate good analysis.
Should have the ability to debug and problem solving and the candidate should be self-driven.
The selected candidate would be working on one or more aspects of the development of Design Ware family of synthesizable cores.
The core areas includes Specification, Architecting, Design, Verification and Release engineering for Synopsys IP products.
The candidate would be assigned to work on either the design or verification tasks and will be part of a global team of expert Design/Verification Engineers.
Company Profile:
Synopsys is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, IP and services used in semiconductor design and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and FPGA solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results.
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